1. Field of the Invention
The present invention relates to a signal transmission circuit and, particularly, to a signal transmission circuit of which output amplitude is variable.
2. Description of Related Art
With the advancement of LSI (Large-Scale Integrated circuit) manufacturing technology, a high-performance MPU (Micro Processor Unit) with the operating frequency of 1 GHz or higher has been developed. When such a MPU is used in information processing equipment, particularly in a server/workstation, high-speed and high-volume data transmission is required. In order to satisfy such requirement, a technique of connecting a MPU and memory modules via PTP (point-to-point) links using FB-DIMM (Fully Buffered Dual Inline Memory Module) is used, for example. The FB-DIMM architecture uses an AMB (Advanced Memory Buffer) chip for connection between memory modules in addition to a memory chip, and it employs high-speed serial interface specification “FB-DIMM High Speed Differential PTP” as a connection interface.
In the high-speed transmission, it is generally necessary to enlarge the output amplitude at the transmitting end in consideration of decay in the amplitude due to a transmission line length. However, if the output amplitude at the transmitting end is uniformly large, power consumption of a chip becomes high. To avoid this, the above interface specification allows the output amplitude to be variable according to a transmission distance. Specifically, if a transmission distance between a MPU and a memory module is relatively long, the amplitude is set to be large; on the other hand, if a transmission distance between a memory module and a memory module is relatively short, the amplitude is set to be small.
In order to make the output amplitude variable, a technique of controlling a current source of a driver is used. A specific example of such a technique is described herein with reference to FIG. 7.
The circuit shown in FIG. 7 includes a constant voltage circuit 4, a constant current circuit 2B, and a differential driver circuit 3. The constant voltage circuit 4 is a bandgap reference circuit that generates a constant voltage from a bandgap voltage of a semiconductor, and it generates a stable constant voltage having a reference amplitude.
The constant current circuit 2B includes P-channel MOS transistors 9 and 10, a P-channel MOS transistor 15, a terminating resistor 16, and a feedback amplifier 17. The P-channel MOS transistors 9 and 10 are connected with a power supply line 8 and form a constant current source. The P-channel MOS transistor 15 has a gate electrode fixed to a GND (ground voltage) level, so that it is in the ON state. The feedback amplifier 17 has an inverting terminal connected with the constant voltage circuit 4, a non-inverting terminal connected with a node between the P-channel MOS transistor 15 and the terminating resistor 16, and an output connected with a node between the gate of the P-channel MOS transistor 9 and the gate of the P-channel MOS transistor 10. The feedback amplifier 17 controls the gate voltage of the P-channel MOS transistor 9 so that the voltage at the terminating resistor 16 is equal to the voltage having a reference amplitude which is generated in the constant voltage circuit 4. A current corresponding to the reference amplitude is thereby output from the drain of the P-channel MOS transistor 10, which has the same gate voltage as the P-channel MOS transistor 9.
The differential driver circuit 3 includes N-channel MOS transistors 19, 20a, 20b, 20c and 20d that are connected with a ground line 18 to receive a constant current from the constant current circuit 2B and form a mirror circuit; P-channel MOS transistors 22a, 22b, 22c, 22d, 23a, 23b, 23c and 23d that are connected with a power supply line 21 and form a constant current source; a switch circuit 11 that connects the gates of the P-channel MOS transistors 23b, 23c and 23d with the power supply line 21 to turn OFF a corresponding constant current source; a switch circuit 12 that connects the gates of the P-channel MOS transistors 23b, 23c and 23d with the drains of the P-channel MOS transistors 22b, 22c and 22d to turn ON a corresponding constant current source; P-channel MOS transistors 24a and 24b that serve as a switch to output a logic; and terminating resistors 25a and 25b that are connected with the ground line 18. Input terminals 26a and 26b input differential logic signals inside the LSI, and in response to those inputs, a voltage value that is determined by the all current values flowing through the P-channel MOS transistors 23a, 23b, 23c, 23d and the resistances of the terminating resistors 25a and 25b is output as a logic amplitude from output terminals 27a and 27b. A constant current source that is composed of the P-channel MOS transistors 22a and 23a is constantly ON. In the following description, the logic amplitude that is output from the output terminals 27a and 27b is referred to as an output amplitude.
In the circuit having such a configuration, the switch circuit 11 that connects the gates of the P-channel MOS transistors 23b, 23c and 23d with the power supply line 21 and the switch circuit 12 that connects the gates of the P-channel MOS transistors 23b, 23c and 23d with the drains of the P-channel MOS transistors 22b, 22c and 22d are selected in a complementary fashion using a control terminal 13, so that the output amplitude corresponding to the reference amplitude is variable.
A specific example is as follows. For example, the P-channel MOS transistors 15, 24a and 24b are configured to be the same, and the terminating resistors 16, 25a and 25b are also configured to be the same. Further, the channel width size ratio of the transistor groups each constituting a constant current source (i.e. the P-channel MOS transistors 9 and 10, the P-channel MOS transistors 22a to 22d, and the P-channel MOS transistors 23a to 23d) is “5:1”, “1:1:1:1”, “5:1:1:1”, respectively. In such a case, if the reference amplitude that is generated in the constant voltage circuit 4 is 500 mV, the output amplitude from the output terminals 27a and 27b can be 500 mV, 600 mV, 700 mV or 800 mV by controlling the switch circuit 11 and the switch circuit 12 through the control terminal 13. Thus, the circuit in FIG. 7 allows the reference amplitude of 500 mV to be variable in increments of 20%. FIG. 7 shows the case where the P-channel MOS transistors 23b to 23d are all OFF, and the output amplitude from the output terminals 27a and 27b in this case is 500 mV, which corresponds to a current value that is output only from the constant current source that is composed of the P-channel MOS transistors 22a and 23a. 
In this manner, the circuit varies the output amplitude by controlling the P-channel MOS transistors 22b to 22d, and the P-channel MOS transistors 23b to 23d, each constituting a constant current source, by the switch circuit 11 and the switch circuit 12.
Japanese Unexamined Patent Application Publication No. 2006-060320 discloses a circuit that varies the output amplitude by controlling a current source of a driver, just like the circuit of FIG. 7.
FIG. 8 shows an example of the circuit that varies the output amplitude by controlling a current that is input to a driver. The circuit of FIG. 8 includes a constant voltage circuit block 1, a constant current circuit 2C, and a differential driver circuit 3A.
The constant voltage circuit block 1 includes a constant voltage circuit 4 and a voltage divider circuit 35. The constant voltage circuit 4 is a bandgap reference circuit just like the constant voltage circuit 4 in FIG. 7. The voltage divider circuit 35 includes ladder resistors, and it divides the output of the constant voltage circuit 4 by the ladder resistors and outputs a plurality of candidate reference amplitudes to the constant current circuit 2C.
The constant current circuit 2C includes P-channel MOS transistors 39 and 40, a P-channel MOS transistor 45, a terminating resistor 46, a feedback amplifier 47, and an analog selector 36. The P-channel MOS transistors 39 and 40 are connected with a power supply line 38 and form a constant current source. The P-channel MOS transistor 45 has a gate electrode fixed to a GND (ground voltage) level, so that it is in the ON state. The feedback amplifier 47 has an inverting terminal connected with the output of the analog selector 36, a non-inverting terminal connected with a node between the P-channel MOS transistor 45 and the terminating resistor 46, and an output connected with the gates of the P-channel MOS transistors 39 and 40. The feedback amplifier 47 controls the gate voltage of the P-channel MOS transistor 39 so that the voltage at the terminating resistor 46 is equal to the output voltage from the analog selector 36, so that a constant current corresponding to the output voltage from the analog selector 36 is output from the drain of the P-channel MOS transistor 40 having the same gate voltage as the P-channel MOS transistor 39. The analog selector 36 is controlled through a selection terminal 37, and the analog selector 36 selects one from the constant voltage from the constant voltage circuit 4 and a plurality of candidate reference amplitudes from the voltage divider circuit 35 and outputs the selected one to the feedback amplifier 47.
The differential driver circuit 3A includes N-channel MOS transistors 49 and 50 that are connected with a ground line 48 to receive a constant current from the constant current circuit 2C and form a mirror circuit, P-channel MOS transistors 52 and 53 that are connected with a power supply line 51 and form a constant current source, P-channel MOS transistors 54a and 54b that serve as a switch to output a logic, and terminating resistors 55a and 55b that are connected with the ground line 48. Further, an output terminal 57a and an output terminal 57b are respectively connected between the P-channel MOS transistor 54a and the terminating resistor 55a and between the P-channel MOS transistor 54b and the terminating resistor 55b. Input terminals 56a and 56b input differential logic signals inside the LSI, and in response to those inputs, a voltage value that is determined by the current flowing through the P-channel MOS transistor 53 and the resistances of the terminating resistors 55a and 55b is output as a logic amplitude from output terminals 57a and 57b. 
In this configuration, the circuit employs the selection terminal 37 as a switch to select a desired reference amplitude from the voltage divider circuit 35, thereby varying the output amplitude of the differential driver circuit 3A.
For example, the P-channel MOS transistor 45 and the P-channel MOS transistors 54a and 54b are configured to be the same, and the terminating resistor 46 and the terminating resistors 55a and 55b are also configured to be the same. Further, the N-channel MOS transistor 49 and the N-channel MOS transistor 50 are configured to be the same. The channel width size ratio of the transistors constituting a constant current source (i.e. the P-channel MOS transistors 39 and 40 and the P-channel MOS transistors 52 and 53) is set to “5:1:1:5”. In such a case, if the reference amplitude generated in the constant voltage circuit 4 is 500 mV, and the voltage dividing ratio of the ladder resistors of the voltage divider circuit 35 is incremented in steps of 5%, the output amplitude from the output terminals 57a and 57b is variable in decrements of 5%, such as 500 mV, 475 mV, 450 mV, 425 mV and so on.
A margin test is sometimes conducted during the shipping test of products in order to ensure that there is no problem about manufacturing fluctuations or characteristics change due to degradation over time. Because the operating frequency of testing equipment such as a LSI tester is relatively low, like several hundreds of MHz, it is general to perform a loopback test or an end-to-end test with the use of an actual device in the high-speed actual operation test. The test may include checking whether a signal can be received correctly by reducing the output amplitude on purpose, and it is thus preferred to apply the structure that makes the output amplitude variable to such a test as well.
Further, as recent memory modules offer high performance, it is necessary to set the output amplitude corresponding to a trace difference in signal lines on DIMM in consideration of the amplitude decay due to a trace difference in signals line on DIMM. Thus, the output amplitude should be large in the lane with a long signal line trace, and the output amplitude should be small in the lane with a short signal line trace. Therefore, an AMB chip to be mounted in such DIMM needs to have the structure that enables the setting of a different output amplitude for each lane.
In order to implement the above structure in the signal transmission circuit having a plurality of lanes with the use of the circuit shown in FIG. 7, it is necessary to place the same number of pairs of the constant current circuit 2B and the differential driver circuit 3 as the number of lanes, which causes an increase in packaging area and power consumption. Further, in order to adjust the output width of each lane during the margin test, it is necessary to configure setting for each lane, thus taking a long time for the setting of the margin test.
Likewise, in order to implement the above structure in the signal transmission circuit having a plurality of lanes with the use of the circuit shown in FIG. 8, it is necessary to place the same number of units from the voltage divider circuit 35 to the differential driver circuit 3A as the number of lanes, which also causes an increase in packaging area and power consumption. It also takes a long time for the setting of the margin test.